Abstract: A new network switch architecture, hybrid circuit switched (HCS), is developed for multi processor systems, which solves the problems of over power and low throughput in on chip network systems (NoC). However, in HCS, to ensure the consistency of each core data, the broadcast is adopted to solve the cache consistency problem. This may occupy many system resources, and have a greater impact on system execution. Therefore, in this paper, we try to solve this problem by discussing the implementation of cache consistency on HCS based chip multiprocessor (CMP), and propose a reliability protocol modeling method based on k-terminal model. Three cache consistency protocols, writeonce, MESI and MOESI, are studied, and the expressions of system reliability probability are obtained. The results show that the reliability of these protocols is improved by 40.22% and 59.83% on average in HCS networks compared with elastic buffer (EB) networks and bus networks.

Key words: cache coherence, networking switch, system reliability, k-terminal model